Dr. Soh Yun Siah,
Technology Vice President,
Technology Development Department
GLOBALFOUNDRIES, Singapore
Title: Heterogeneous Integration of GaN and Silicon for Power Conversion
Abstract
Gallium Nitride (GaN) power devices offer significant system-level performance advantages over silicon power devices for many power conversion applications. In recent years, there has been rapid progress toward addressing the key barriers to wide-spread adoption of GaN power, including technology maturity, reliability, manufacturability, and cost. Another challenge that is receiving significant attention is the integration of GaN power devices along with control circuitry to enable power supplies in package with optimized system cost and performance. This presentation will compare several approaches to GaN/silicon integration, including a review of published materials and original work performed by GLOBALFOUNDRIES and affiliates. In one approach, wafer-to-wafer bonding is employed to enable full 200mm wafers that include silicon CMOS control circuitry and GaN power devices interconnected using standard CMOS backend metallization. In another approach, die-to-wafer bonding is used to integrate GaN power transistors on top of silicon bipolar-CMOS-DMOS (BCD) wafers. The presentation will include previously unpublished results from several successful technology demonstrators, including DC-DC converters that comprise silicon BCD control circuits and GaN power output stages.
Biography
Soh Yun Siah is a Technology Development Vice President at GLOBALFOUNDRIES with over 20 years of semi-conductor experiences. She has served multiple senior positions in Chartered Semiconductor Mfg and GLOBALFOUNDRIES SINGAPORE since 1996 after receiving her Ph.D. in Science from National University of Singapore. She is currently in charge of GLOBALFOUNDRIES SINGAPORE Technology Development Department. She oversees the technology roadmap execution and drives differentiation to enrich the foundry technology portfolio. Over the years, her contributions span over multiple CMOS technology node generations. In recent years, she led technology development in More-than-Moores specialty technologies (non-volatile memories, high voltage, power-analog applications etc). She has published over 30 technical papers and holds over 15 granted patents.
Jame T. Doyle, PE, Dialog Semiconductor, U.S.A.
jim.doyle@diasemi.com
Title: A 100Mhz 8 Ampere 4 Phase Buck with 87% Efficiency Using a Low Cost Semiconductors and ICs, and chair of the EDS Technical Committee on Power 0.13u Process Providing Power for Mobile CPU and GPU and Evolution to Inductors on Die
Abstract
An IVR developed for SiP integration with a mobile SoC is presented, including key design requirements, challenges, and solutions. Results from 1st generation silicon, utilizing co-packaged inductors (0402 footprint, <0.2mm height) and co-packaged capacitors (0201 silicon caps, <0.1mm height), will be provided. Learning from this design is being incorporated into a 2nd generation design that utilizes fully integrated on-die inductors based on inductor structures available from TSMC. Early results from the 2nd generation design will be included.
The architecture presented is modular, enabling a highly flexible implementation. The talk will cover all aspects of the final solution including sip package, boards, and chip design considerations. The design operates in a conventional type 3 voltage mode using K factor methodology with on die tuning for stability. It achieves the target bandwidth (10Mhz) and correspondingly fast DVS (>5 volts/us). The target switching frequency is 78MHz which is the 3rd harmonic phase-locked to a 26MHz system clock. Additionally, spread spectrum operation is supported for EMI mitigation. All key blocks will be covered in this talk.
The overall design is part of a 2-stage architecture where stage 1 can be external while the stage 2 is integrated (either in-package or on-die). Such integration supports improved system regulation and second droop rejection. The performance and regulation of the stage 1 is not as critical as a traditional single stage design. This architecture also has the additional benefit of lowering package current and freeing up package balls. By implementing the IVR in a low cost 0.13u BCD process, the stage 1 may be integrated onto the same die as the IVR, further reducing cost and size.
Biography
Mr. James T Doyle, PE., has over 45 years of experience with the leading semiconductor providers in the industry including Intel, Qualcomm, Motorola, National Semiconductor. His present position is Member of the Technical Staff at Dialog Semiconductor, heading up high speed 2-stage integrated voltage regulator architectures which include integrated on-die inductors and silicon capacitors. Mr. Doyle in his previous capacities has been a design manager and SMTS at Intel, Motorola, and National Semiconductor. He lead IVR work at Intel “Bangor” project circa 2007, and 4 generations of embedded VR technology at Qualcomm up to 7 nanometers process node. Mr. Doyle has over 100 patents and co-authored 10 technical publications. He is also an Adjunct Professor at Embry Riddle Aeronautical University teaching communications theory.
Peng Zou, Huawei, PHisilicon Semiconductor Co., Ltd. a Huawei Company, Shenzhen, China
Peng.zou@huawei.com
A 100MHz IVR PMIC with On-silicon Magnetic Thin Film Inductors
Peng Zou, Song Wei, Xie Qiang, Chen Liang, Chen Yue, Huang Chen, Wang Jiake, Wang Xinyu, Shen Zhongguo, Cui Xiaojuan
Hisilicon Semiconductor Co., Ltd. A Huawei Company, Shenzhen, China
Abstract
We will report the design and fabrication of a 100MHz IVR power management IC in WLCSP package with on-silicon magnetic inductors. Highly modularized multiphase buck converter circuit architecture was developed for integrated coupled inductors, and achieved the state of art load transient performance and accurate phase current balancing. The integrated on-silicon inductors are fabricated using proprietary process compatible with volume wafer level package technology. It is believed to be the first integrated magnetic IVR chip realized in WLCSP form, and it demonstrated that the volume WLCSP process flow can accommodate integrated magnetic inductor after incorporating necessary process tuning. Additionally, some results of the system testing with SoC running performance benchmark programs will be shared to show the potentials of adopting integrated magnetics IVR technology.
Our perspective on the road toward commercializing on-silicon magnetics will be presented to shed the light on the challenges and opportunities in end user adoption, industry-wise technological readiness, and supply-chain challenges. Our take on the gaps in current R&D efforts in the field of on-silicon magnetics will be discussed, and potential research areas to advance this field to meet the increasingly difficult power density problem as semiconductor industry continue scaling up transistor density.
Biography
Peng Zou received the B.S.E.E. and M.S.E.E. degrees from University of Electronic Science and Technology of China in 1991 and 1994, respectively, and the Ph.D. degree of Electrical Engineering from Illinois Institute of Technology, Chicago, Illinois, USA, in 2001.
He joined Hisilicon Technologies Co., Ltd. a Huawei Company in 2014 as a senior technologist leading the R&D of integrated voltage regulator technology. He has been working with a cross-discipline engineering team to productize on-chip magnetic inductor based IVR, and is involved in every aspect of the effort from chip architecture, analog design, on-chip magnetic thin-film inductor development, and volume manufacture strategy and enabling.
He was an IC design engineer with Intel Corporation, Hillsboro, Oregon, USA, from 2002 to 2014, where he designed high speed IO and high frequency integrated voltage regulator related IC circuitry. He was involved in Intel’s IVR path-finding project, “A 400 Amp Fully Integrated Silicon Voltage Regulator with In-die Magnetically Coupled Embedded Inductors,” as one of the core contributors.
Louis Chen, ASE, Taiwan
Title: New Generation Power Packaging Technology
