PwrPACK 2019 Key Note Speakers




Keynote #1 Integration Session

PwrSoC Workshop – A Perspective of PwrSoC Progress
Cian O’Mathuna, Tyndall National Institute, Ireland


The concept of fully integrated dc-dc conversion and voltage regulation has been discussed in both industry and academia for more than a decade. Currently, the major challenge being addressed by many companies is the miniaturization and integration of bulky inductor components in dc-dc converters for power delivery to micro-processors and systems-on-chip (SoC) in electronic systems These inductors can take up to 50% of the power management footprint on the motherboard, introduce an unacceptable height profile, add to the bill-of-materials cost and introduce circuit parasitics which impact power efficiency and high-speed transient performance. Commercial solutions for monolithic integration of thin-film magnetic-core inductors continue to be explored by a number of companies, the major roadblocks being the availability of high volume foundry capability and high frequency power management ICs. Some companies have stepped back from the monolithic solution and are exploring inductor integration into or on top of the processor package or substrate. Other companies are exploring the alternative use of air-core inductors. This presentation will explore the progress and evolution of the PwrSoC concept. Special attention will be given to the opportunities and challenges that exist for the OSAT and package substrate industries in the evolving technology roadmap.  


Prof O’Mathuna has more than 30 years’ experience in applied research and technology transfer to Irish and international industry. His research is focused on the convergence of microelectronics and microsystems to address the future technological challenges that will enable the 1 trillion sensor economy.  Cian is Head of Centre for MicroNano Systems at Tyndall which is focused on developing a fundamental understanding of how to interface intelligent, autonomous microelectronic systems:

  • with the built and the natural environment to improve the sustainability of our natural resources and the quality of our environment through monitoring and control and

  • with the human body to enhance our health and well-being through wearable and in-vivo diagnostics and therapeutics

Cian has been a co-founding member of national industry-academic research clusters in the areas of surface mount technology (Smart Group Ireland), wireless sensor networks (WiSEN) and power electronics (PEIG). In 2010, he was an Irish Government appointee on the National Innovation Task Force Implementation Group. He is a Research Professor in the College of Engineering, University College Cork. Cian has been associated with the PSMA for more than 20 years as a Board Member and as Co-Chair of the Packaging Committee. In 2008, he founded the International Workshop on Power Supply on Chip (PwrSoC) which is now the PSMA and IEEE flagship conference in this space. As a result, Prof. Ó Mathúna is recognized by the global semiconductor community for his thought-leadership in articulating and driving a vision to deliver the “holy grail” for fully-integrated power management of electronic systems, “Power Supply-on-Chip” (PwrSoC). In January 2013, he was named an IEEE Fellow in the field of power electronics.

Keynote #2 Packaging Session

Advanced Packaging Architectures for Heterogeneous Integration

 Ravi Mahajan, Intel Fellow, Intel  Corporation.


In recent years advanced packaging technologies have gained considerable attention because of their importance as compact, power-efficient platforms for heterogeneous integration (HI).  This talk will trace the evolving role of packaging over the past decades and examine its value as a HI platform.  Different packaging architectures will be compared primarily based on their physical interconnect capabilities.  Key features in leading-edge 2D and 3D technologies, such as EMIB, Silicon Interposer, Foveros and Co-EMIB will be described and a roadmap for their evolution will be presented.  The talk will conclude with a discussion of opportunities and challenges in driving the package roadmap forward.



RAVI MAHAJAN is an Intel Fellow and the Co-director of pathfinding in assembly and packaging technologies for 7-nanometer (7nm) silicon and beyond in the Technology and Manufacturing Group at Intel Corporation. He is responsible for planning and carrying out multi-chip package pathfinding programs for the latest Intel process technologies, led efforts to define and set strategic direction for package architecture, technologies and assembly processes at Intel since joining the company’s Assembly and Test Technology Development organization in 2000, spanning 90nm, 65nm, 45nm, 32nm, 22nm, and 7nm silicon. Earlier in his Intel career, he spent five years as group manager for thermal-mechanical tools and analysis.

A prolific inventor and recognized expert in microelectronics packaging technologies, Mahajan holds more than 30 patents, including the original patent for a silicon bridge that became the foundation for Intel’s Embedded Multi-Die Interconnect Bridge technology. His early insights also led to high-performance, cost-effective cooling solutions for high-end microprocessors and the proliferation of photo-mechanics techniques used for thermo-mechanical stress model validation. Ravi has written several book chapters and more than 30 papers on topics related to his area of expertise.

Ravi joined Intel in 1992 after earning a bachelor’s degree from Bombay University, a master’s degree from the University of Houston, and a Ph.D. from Lehigh University, all in mechanical engineering. His contributions during his Intel career have earned him numerous industry honors, most recently the SRC’s 2015 Mahboob Khan Outstanding Industry Liaison Award, the 2016 THERMI award from SEMITHERM and the 2016 Allan Kraus Thermal Management Medal from the American Society of Mechanical Engineers. He has also been nominated as an IEEE EPS Distinguished Lecturer.  He is one of the founding editors for the Intel Assembly and Test Technology Journal (IATTJ) and currently Co-Editor for Special Topics of IEEE T-CPMT.  Additionally, he has been long associated with ASME’s InterPACK conference and was Conference Co-Chair of the 2017 Conference.  Ravi is a Fellow of two leading societies, ASME and IEEE.  He was named an Intel Fellow in 2017.