Plenary Sessions

Wednesday, September 24th, 10:00 AM

Innovations in Power Delivery to Meet Power Demands of High-Performance GPU Demands

AI scaling laws are driving a rapid increase in datacenter GPU power, which is projected to surpass 5KW before the end of the decade. Evolutionary MBVR based solutions are unlikely to support the current density and bandwidth demands of these high-power systems. In this talk, we will explore the development of Integrated Voltage Regulator (IVR) solutions that deliver high current density and bandwidth. We will look at different IVR architectures and the passive technologies required to enable them. We will also look at different package integration schemes the associated thermal and mechanical challenges.

Dr. Kaladhar Radhakrishnan Intel Fellow, Intel, U.S. Kaladhar Radhakrishnan is an Intel Fellow and a Power Delivery Architect with the Technology Development group at Intel. He has played a significant role in shaping and driving power delivery technologies for Intel microprocessors. His areas of expertise are in integrated voltage regulators, advanced packaging and passives technologies. Kaladhar is a two-time recipient of the Intel Achievement Award. He has authored four book chapters, over 50 technical papers in peer reviewed journals, and has been awarded 40 US patents. Kaladhar joined Intel in 2000 after he received his Ph.D. in Electrical Engineering from the University of Illinois at Urbana-Champaign.

Wednesday, September 24th, 11:20 AM

Breaking Limit in Power Delivery : BSPDN and Its Synergy with DTCO Innovations

Backside Power Delivery Network (BSPDN) is a disruptive innovation that addresses the growing challenges of power delivery in advanced logic scaling. By relocating power rails to the backside of the wafer, BSPDN decouples power and signal routing, enabling relaxed front-side metal pitch, reduced cell height, and enhanced routing flexibility. These architectural changes provide substantial benefits in power, performance, and area (PPA), while also reducing BEOL resistance and IR drop. From a Design-Technology Co-Optimization (DTCO) perspective, BSPDN opens new opportunities to push the limits of logic density and efficiency without aggressive front-side scaling. The Samsung Foundry’s latest 2nm process, SF2Z, integrates an optimized BSPDN structure, achieving notable improvements in comparison to the SF2 node. In particular, SF2Z delivers enhanced voltage stability and significant performance gains in high-performance computing (HPC) applications. BSPDN, in synergy with DTCO innovation, is expected to play a pivotal role in shaping the future of power delivery and logic scaling in the sub-2nm era.

Dr. Byung-Sung Kim Vice President of Technology, Samsung Electronics, South Korea Byung-Sung Kim is a Master (VP of Technology) of Logic Technology Development Team at the Semiconductor R&D Center of Samsung Electronics. He currently leads technology enablement for advanced technology, including design technology co-optimization (DTCO) and design rule development. He began his career at Samsung Electronics in 2005, initially working on lithography process development before transitioning to logic technology development. He received a Ph.D., M.S. and B.S. in Materials Science and Engineering from Seoul National University in Korea.

Thursday, September 25th, 9:00 AM

It’s Too Noisy! Issues with Voltage Noise in AI Workloads and Strategies to Minimize It

	Dr. Tezaswi Raja Senior Director of Engineering, Nvidia, U.S.