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Session November 5, Speakers |
Session November 10, Speakers |
Session November 12, Speakers |
System-Level Power Management Strategies for Integrated Platforms
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Vivek De |
Abstract
Future “smart and connected” systems demand compact compute/communication platforms that can provide uncompromising on-demand performance and user experience with maximum energy efficiency across a variety of workloads and applications under stringent thermal and power delivery constraints. We will present key trends in holistic system level power delivery/management featuring (1) fine-grain multi-voltage SoC design; (2) fast & efficient wide-range DVFS; (3) workload-dependent dynamic power budget allocation; (4) fast & efficient shut-down/wake-up; and (5) self-adaptation to variations. An overview of the key challenges and latest advances in architecture, design, and process/package for realization of monolithic & heterogeneous 2D/3D-integrated compact, efficient, low supply noise, fine-grain, high-bandwidth & fast-response power converters & voltage regulators across a wide range of input/output voltages & load currents for digital logic/memory & analog/mixed-signal building blocks in SoCs will also be presented. These capabilities are essential for implementing intelligent system-level power management and adaptation schemes across hardware and software.
Biography
Vivek De is an Intel Fellow and Director of Circuit Technology Research in Intel Labs. He is responsible for providing strategic technical directions for long-term research in future circuit technologies and leading energy-efficiency research across the hardware stack. He has 315 publications in refereed international conferences and journals with a citation H-index of 80, and 229 patents issued with 32 more patents filed (pending). He received an Intel Achievement Award for his contributions to an integrated voltage regulator technology. He is the recipient of the 2019 IEEE Circuits and System Society (CASS) Charles A. Desoer Technical Achievement Award for “pioneering contributions to leading-edge performance and energy-efficient microprocessors & many-core system-on-chip (SoC) designs” and the 2020 IEEE Solid-State Circuits Society (SSCS) Industry Impact Award for “seminal impact and distinctive contributions to the field of solid-state circuits and the integrated circuits industry”. He received a Best Paper Award at the 1996 IEEE International ASIC Conference, and nominations for Best Paper Awards at the 2007 IEEE/ACM Design Automation Conference (DAC) and 2008 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). He also co-authored a paper nominated for the Best Student Paper Award at the 2017 IEEE International Electron Devices Meeting (IEDM). One of his publications was recognized in the 2013 IEEE/ACM Design Automation Conference (DAC) as one of the “Top 10 Cited Papers in 50 Years of DAC”, and another one received the “Most Frequently Cited Paper Award” in the IEEE Symposium on VLSI Circuits at its 30th Anniversary in 2017. He received the 2017 Distinguished Alumnus Award from the Indian Institute of Technology (IIT) Madras. He received a B.Tech from IIT Madras, India, a MS from Duke University, Durham, North Carolina, and a PhD from Rensselaer Polytechnic Institute, Troy, New York, all in Electrical Engineering. He is a Fellow of the IEEE.
Integrated Voltage Regulators for 3D ICs
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Noah Sturcken |
Abstract
Modern high-performance computing (HPC) processors are increasingly constrained by power integrity and package power handling capability. Integrated voltage regulators (IVRs) can alleviate these constraints but must meet demanding requirements for integration, current density, regulation, efficiency, quality and cost in order to legitimately add value to next generation HPC systems. Additionally, addressing a diverse set of SoC load-requirements, covering CPUs, GPUs, FPGAs, ADCs, PLLs etc. requires a corresponding set of power conversion and regulation options all the while maintaining compatibility for integration with the load. This talk will discuss advances in IVRs addressing future HPC systems, which are increasingly adopting chip-on-wafer and wafer-on-wafer integration schemes to achieve performance and manufacturing gains.
Biography
Noah Sturcken has focused on the integrated power conversion with CMOS for over a decade. Dr. Sturcken is a founder and CEO of Ferric, which sells integrated voltage regulator products and related technologies. Dr. Sturcken holds a PhD from Columbia University and has over 25 publications and patents, primarily related to CMOS integrated power conversion.
Prospective Applications for PwrSoC
Magnetics and Packaging Technologies
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Seamus O’Driscoll |
Abstract
Packaging and magnetic component designs appropriate for PwrSoC and PwrSiP are considered from an applications perspective. The micro-power PMIC is generally challenged by requiring a larger inductance value to enable low current ripple while the higher power Point-of-Load (POL) or Resonant converter is challenged by the requirement for a larger current handling ability. We explore how thin-film and substrate-embedded magnetic devices with high-Q can address the integrated filter inductor challenges. Thin-film and embedded coupled-winding solutions are examined for use in an eSiP (energy harvesting source-in-package) for the self-powered IoT sensor node. The integrated magnetic device features in various solutions for ultra-low voltage cold start; cross-coupled LC resonant tank, Meissner oscillator or Boost with coupled gate feedback. Magnetic isolation technologies for the next generation integrated smart gate-drivers are presented.
Biography
Séamus is currently Principal Investigator for Integrated Power Systems at Tyndall National Research Institute and MCCI. He is leading a number of research themes spanning ULP PMIC, Isolated PwrSiP converters, Smart Gate Drivers and Point-of-Load DC-DC, with all employing thin film magnetics-on-silicon or substrate embedded magnetic solutions.
Earlier career roles have included Power Control Silicon Systems Architect with Texas Instruments Ltd. and Corporate Technology Staff Engineer with Artesyn Technologies Ltd. He has released many professional power product designs to the world’s leading communications and computer companies.
Faster, Higher, Monolithic –Efficient Energy Conversion with GaN
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Bernard Wicht |
Abstract
As a wide-band gap material, GaN (gallium nitride) offers a huge potential to reduce the overall power electronics system size and cost. However, parameters such as common-mode transient immunity (CMTI) and minimum parasitic gate loop inductance become more challenging, as they degrade the fast-switching performance. This talk presents innovations on system and circuit level related to GaN. The concept of high-voltage energy storing (HVES) enables highly integrated gate driver designs, which can even utilize the parasitic gate loop inductance for a resonant gate drive approach. Monolithic GaN-on-Si integration reduces the gate loop inductance nearly to zero and allows for integration of a power converter along with the control loop on a single die. A 400V offline GaN IC will be presented, which achieves superior efficiency and power density along with lowest component count.
Biography
Bernhard Wicht has 20+ years of experience in analog and power management IC design. He received the Dipl. Ing. degree in electrical engineering from University of Technology Dresden, Germany, in 1996 and the Ph.D. degree (Summa Cum Laude) from University of Technology Munich, Germany, in 2002. Between 2003 and 2010, he was with Texas Instruments, Freising, responsible for the design of automotive power management ICs. In 2010, he became a full professor for integrated circuit design and a member of the Robert Bosch Center for Power Electronics at Reutlingen University, Germany. Since 2017, he has been heading the Chair for Mixed-Signal IC Design at Leibniz University Hannover, Germany. His research interest includes IC design with focus on power management, gate drivers and high-voltage. Dr. Wicht was co-recipient of the 2015 ESSCIRC Best Paper Award and of the 2019 First Prize Paper Award of the IEEE Journal of Emerging and Selected Topics in Power Electronics. In 2018, he received the faculty award for excellent teaching at his university. He invented seventeen patents with several more pending. He is currently a member of the Technical Program Committee of ISSCC and he is also a Distinguished Lecturer of the IEEE Solid-State Circuits Society.
Integrated Hybrid Converters for Mobile and IoT Applications
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Patrick Mercier |
Abstract
The increasing battery life demands of mobile and IoT devices in increasingly restricted board area is putting immense pressure on power management components to simultaneously improve efficiency and power density. Since the power processing capability of inductors is not scaling commensurate with application demands, there has been recent significant interest in augmenting the capabilities of inductive converters with the capabilities of switched-capacitor converters, towards the development of hybrid converters. This presentation will describe several different types of hybrid converters, including a Li-ion-compatible 4-level flying-capacitor multi-level converter and a hybrid single-inductor multi-output (H-SIMO), both integrated into 28nm FDSOI and optimized for achieving high efficiency in a small volume over a large dynamic range of load currents for IoT systems. For mobile systems, we will describe a symmetric multi-level ladder and inductor-first 3rd order buck converters that are optimized for maximizing the trade-off between efficiency and power density at high load currents.
Biography
Patrick Mercier is an Associate Professor of Electrical and Computer Engineering and co-founder/co-director of the Center for Wearable Sensors at UC San Diego. He received his B.Sc. degree from the University of Alberta, Canada, in 2006, and the S.M. and Ph.D. degrees from MIT in 2008 and 2012, respectively. Prof. Mercier has received numerous awards, including the San Diego Engineering Council Outstanding Engineer Award in 2020, a National Academy of Engineering Frontiers of Engineering Speaker in 2019, the NSF CAREER Award in 2018, the Biocom Catalyst Award in 2017, the UCSD Academic Senate Distinguished Teaching Award in 2016, the DARPA Young Faculty Award in 2015, the Beckman Young Investigator Award in 2015, The Hellman Fellowship Award in 2014, the International Solid-State Circuits Conference (ISSCC) Jack Kilby Award in 2010, amongst others. He has published over 130 peer-reviewed papers in venues such as Nature Biotechnology, Nature Communications, ISSCC (17 papers), Advanced Science, and others. He is an Associate Editor of the IEEE Transactions on Biomedical Circuits and Systems and the IEEE Solid-State Circuits Letters, is a member of the ISSCC, CICC, and VLSI Technical Program Committees, and has co-edited three books: High-Density Integrated Electrocortical Neural Interfaces (Elsevier Academic Press, 2019), Power Management Integrated Circuits (CRC Press, 2016), and Ultra-Low-Power Short-Range Radios (Springer, 2015). His research interests include the design of energy-efficient mixed-signal systems, RF circuits, power converters, and sensor interfaces for wearable, medical, and mobile applications.
Integrated Power Management for Wearable Applications:
Opportunities & Challenges
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Cristiano Azzolini |
Abstract
The recent large growth of consumer electronics segments like wearable and edge-computing leads the requirements of power-management ICs (PMICs) to extreme complexity, mixing advanced performances and consumer-market driven costs into a very competitive landscape. These ingredients highlight the need for increased integration of PMICs at very fast pace, including at device, IC and solution level. The talk will address some of the innovative solutions for highly-integrated PMICs to overcome the main challenges.
Biography
Cristiano Azzolini, MSc EE (2003), PhD EE (2006), joined Dialog Semiconductor in 2010, covering different roles in the engineering R&D team dedicated to design of new IP concepts/architectures for PMIC mobile applications. He is currently Engineering Director of System Architecture and IP Group of Dialog Semiconductor, Custom-Mixed-Signal Business Group. His technical background is on design of analog/mixed-signal ASICs for sensors and highly integrated power management ICs with current focus on the definition of custom PMICs and advanced IPs for mobile, wearable and wide consumer applications.
Current Commercialization Activities for Wafer level Magnetics
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Trifon Liakopoulos |
Abstract
Historically wafer level magnetics were pursued for dedicated fully integrated voltage regulators operating at extremely high switching frequencies ≥ 80 MHz but more recently wafer level magnetics are developed across a wide spectrum of market applications to include both inductor and transformer applications which in turn requires obtaining higher values of inductances and higher values of operating current. With recent advances that reduce switching losses by improvements in semiconductor devices, device packaging and circuit topologies, the operating frequency range that wafer level magnetics has expanded to include frequencies as low as 10 MHz. This presentation will address recent advances in different fabrication methods for wafer level magnetics which include front-end-of-line (FEOL) which include sputtering and vapor deposition, back-end-of-line (BEOL) which includes electroplating and hybrid techniques combines either FEOL processes or BEOL processes with packaging techniques such as wire bonding etc., As part of this discussion a survey of the operating parameters addressable by various 2D magnetic core with 3D conductors and 3D magnetic core with 2D conductor will be discussed towards the end goal of identifying the expanding applications that are becoming addressable by wafer level magnetic
Biography
Trifon is a recognized Wafer Level Magnetics industry pioneer and an award winning product innovator. Prior of founding EnaChip and in addition to his experience with large corporations such as Bell Labs and Altera, Trifon co-founded Enpirion (acquired by Altera and now Intel) a world leader in power integration as a spinout from Bell Labs to successfully commercialize the world’s first Power System on Chip (PwrSoC) products for consumer and industrial markets. He led the development efforts of magnetic MEMS technology, set up wafer process prototype labs and established a technology platform for PwrSoC device manufacturing. Trifon was responsible for all aspects of product development and commercialization including design, product manufacturing and cost analysis and he managed the supply chain and all outsourced activities including all foundry partnerships and relationships. He is now focusing growing Enachip as a unique world leading company offering integrated magnetic technologies and solutions for PwrSoC and medical device industries by leveraging cutting edge proprietary MEMS and nano-technology materials and processes. He has several publications; he served 5 years as a member of the Board of Trustees at the University of Ioannina-Greece and holds 21 patents.
Technical Trend and Future Perspectives of
Capacitive Devices for Micro Processor
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Shunsuke Abe |
Abstract
Power delivery for microprocessors is getting attention as one of the biggest roadblocks. First, various solutions, not only decoupling capacitor but integrated VR and in-package power inductor, are summarized. With the end of the Dennard Scaling, memory bottleneck take us to the new paradigm of higher band width and higher wiring density, which bring about IR droop,
and require spatially temporally fine grained power control to mitigate power and heat concentration problems. To achieve these function, integration of several non-active devices with heterogeneous packaging trends and interconnect technologies also have to be taken into account. This presentation reveals some of our research work and propose new solutions to these problems from passive maker’s viewpoint and our constraints.
Biography
ABE received the B.S. degree in material physics, electrical engineering in 2006, the Master of Engineering in 2009 from the University of Tohoku, Japan. He has worked for murata manufacturing as the R&D of multilayer ceramic capacitor, then the manager of business development. He running several projects to create low profile multi terminal capacitor, PDN modeling to offer the benefit for heterogeneous packaging, High Q factor RF matching inductor for sub 6GHz range, ceramic antenna array for wireless power transmission, 3D WLP packaging technology etc. He also has the interests in integrated voltage regulator, switched-cap converter, energy harvesting for edge AI systems.
Trends for Integrated Isolated DC/DC Conversion in Automotive Applications
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Jeffrey Morroni |
Abstract
Automotive applications are seeing a significant increase in connectivity and functionality. With this increase comes new challenges for power management, especially in the context of EV/HEV where high voltages are also present. Specifically, with high voltages comes the added requirements around safety and isolation. This talk will summarize these trends and challenges as well as introduce technologies solutions for integrated, isolated DC/DC conversion in automotive. By achieving fully integrated, isolated DC/DC conversion, new electric vehicle power distribution architectures with significant advantages can be enabled.
Biography
Dr. Jeffrey Morroni is currently Director of Power Management R&D for Kilby Labs, Texas Instruments corporate R&D group. In this role, Dr. Morroni is responsible for driving the overall power management technology strategy within Texas Instruments in collaboration with the businesses and technology manufacturing groups. Prior to this role, he was a researcher in Kilby Labs focusing on a variety of topics including high frequency switchers, on-chip passive integration, LED drivers and CPU power. Dr Morroni joined Texas Instruments in 2011 through the acquisition of National Semiconductor. He graduated from The University of Colorado at Boulder with his PhD. in power electronics and has numerous patents and peer reviewed publications.
