Ted DiBene
Intel
USA
Power delivery for advanced platforms, from consumer electronics to large servers is becoming very challenging. Sophisticated power management on these platforms, particularly in the high power devices, has been ongoing for some time but much, much more is needed. Until very recently, the problems with on-die power delivery have resulted in low current and low efficiency indicating that it might be a while before this technology was mature enough to be introduced into products. However, this has now changed. This presentation will illustrate some of the platform level challenges and will then discuss in detail a technology that has broken the mold in on-die power delivery with magnetics and will show a device that has the capability of powering an entire server platform with a device the size of a fingernail.
J. Ted DiBene II is currently a lead silicon power architect at Intel advancing both silicon and system power management. His recent focus has been in power management for microprocessors and other silicon devices including SoC’s. Prior to that, Dr. DiBene was the lead architect and senior technologist for a highly advanced integrated silicon power chip inside of Intel. Along with his background in power he has spent a large portion of this time on system architecture. Prior to working at Intel, Dr. DiBene was the chief technology officer at INCEP Technologies, a startup in San Diego. He has been involved in advanced signal integrity, power system management, and platform research and development since the late 80’s and has brought many products thru the development process over his career. Dr. DiBene holds a BSEE from UC Santa Barbara as well as an MSEE and PhD in Applied Physics and Electrical Engineering from UC San Diego. He holds 26 patents and has authored over 50 papers in the area of power, signal integrity, and thermal. He is an affiliate professor at the University of Washington and spends his spare time volunteering his time to education of bio-diesel and other energy conservation efforts at high schools.
Francesco Carobolante, Ed Stanford, Bruno Allard, José Cobos
Aleksandar Prodic
University of Toronto
Canada
This paper gives a review of emerging digital and mixed-signal control methods and architectures for on-chip integrated dc-dc switch-mode power supplies (SMPS). The paper is divided into three main parts.
First, it discusses practical implementation problems of digital controllers and shows architectures enabling operation of at ultra high switching frequencies (beyond 100 MHz) allowing significant minimization of the power stage components.
The second part addresses dynamic response of controllers and associated problems of the output filter overdesign creating challenges in on-chip integration of the filtering components. In this part mixed-signal control solutions for obtaining minimum output filter size, defined by the physical limitations of a given power stage, is shown. The presented mixed-signal controller does not require any prior knowledge about the components values and, as such, eliminates the need for custom design.
In the final part, load-interactive controllers and advanced SMPS topologies further minimizing the size of the reactive components and improving power processing efficiency are shown. Theoretically, the presented load-interactive solutions allow drastic reduction of the filtering components, such that their size is limited by the output ripple value only.
Aleksandar Prodic is an associate professor at the ECE department of the University of Toronto, where, in 2004, he formed Laboratory for Power Management and Integrated SMPS. He received his Ph.D. and M.Sc. degrees from the University of Colorado in Boulder, and Dipl. Ing. degree from the University of Novi Sad in Serbia.
Alex Vainberg
National Semiconductor
USA
With the emphasis on lowering power consumption a concern for system designers, National Semiconductor has pioneered a technology for reducing the energy consumed by large-scale CMOS ASICs and other digital systems on a chip (SoCs).
This technology is called Adaptive Voltage Scaling (AVS) which can reduce the overall energy consumption by 40% or more. AVS is a closed-loop control system that not only handles process variation between devices, but it also handles shifts in temperature, digital load, and process aging.
B.Sc. of Engineering from Technology Institute in Haifa, Israel
M.Sc. Electrical Engineering from Tel-Aviv University, Israel
Worked on different engineering and management positions at Tower, Jazz Semiconductor, Novelics and National Semiconductor.
Has an expertise in intellectual property development, foundry and mixed-signal design
Breakout Room
Dominik Schmidt
Intel
USA
As geometries scale to 32nm and below, the voltage-handling capability of CMOS systems is coming under increasing strain. The core transistors and SRAM cells are constrained to mV levels, and even the periphery devices no longer offer a dependable interface to system voltages. At the same time, voltage regulation and conversion systems can inject unacceptable noise into the substrate, with ever more complex power routing schemes and ground-plane management. As with other aspects of CMOS scaling, these problems come with opportunities, such as potentially lower power conversion losses due to improved switching, SoC-level quasi-adiabatic power management techniques and increasing integration of regulation sub-systems on the nanoCMOS die. To balance these tradeoffs requires a careful re-assessment of the overall SoC design process, including new EDA tools and circuit techniques.
Dominik Schmidt, M.S.M., Ph.D., PE has been working in the semiconductor industry for 20 years. He earned
his EE doctorate from Stanford in 2003. He was at Altera working in reconfigurable logic and has worked with
Sharp, TI, Cypress and TSMC. He co-founded Pixel Devices International (PDI) in 1997, one of the first
companies to offer CMOS imaging chips. After PDI was acquired by Aglient he founed Airify Communications,
specializing in multi-protocol wireless chip design. Following the acquisition of Airify, Dr. Schmidt is now
Director of Engineering at Intel Corporation, where he is leading the introduction of next generation mixedsignal
processes. He has also worked for the Stanford Linear Accelerator and Lawrence Berkeley National
Laboratory on several advanced projects, and consulted for several large companies and startups in the mixedsignal
and RF design areas. He has taught at UC Extension since 2000 and also taught at Tsinghua University in
Beijing and the Swedish Royal Institute. He is wiring a graduate textbook on RF Design for Elsevier Press. He is
also a Lieutenant with the US Coast Guard.
Hans Meyvaert
ESAT MICAS K.U. Leuven
Belgium
Scaling of CMOS is enabling ever more complex systems to be fully-integrated on a single die, this results in various System on Chip (SoC) designs with advanced functionality available at ever lower processing cost. Transistor supply voltages are low in these advanced CMOS technologies in order to reduce power consumption. At the same time battery supply voltages remain constant or even increase to enable a higher energy density. This creates a gap that cannot be solved by the well known linear regulator technology due to their poor associated efficiency.
Integrated switched-mode DC-DC converters are a much better choice to close this gap in terms of conversion efficiency. As a result, switching converters are able to increase the autonomy in mobile devices, thereby reducing battery constraints. Moreover, they are also crucial in high-end designs such as CPU’ s and SoC’ s by avoiding excess power losses and alleviating thermal issues. Research at the MICAS (K.U.Leuven) laboratory has explored the field of both fully-integrated inductive and fully-integrated capacitive converters. Since 2006 this has resulted in more than 13 prototypes of fully-integrated DC-DC converters in standard CMOS.
In these prototypes various specifications important for DC-DC conversion are targeted. These include high efficiency (up to 88%), low ripple (down to 0.5%), reconfigurability, high power density (213mW/mm2), large conversion ratio (10X) and tight control (PID, hysteretic,…).
This presentation will give an overview of the results produced by the research conducted at MICAS. It will go deeper into the fundamental restrictions of fully-integrated DC-DC converters in standard CMOS. But also the opportunities of on die power management.
Hans Meyvaert was born in Sint-Truiden, Belgium, in 1985. He received the M.Sc. degree in electrical engineering from the Katholieke Universiteit Leuven (K.U.Leuven), Belgium, in 2009.
Currently he is a research assistant at the ESAT-MICAS Laboratory of the same university where he is working towards the Ph.D. degree. His research interest includes on die power management in general and currently capacitive DC-DC converters in specific.
William O. Keese
National Semiconductor
USA
The linearity requirements and complexity of the handset RF Front End to support multimode multi-band architectures place a premium on power amplifier performance. With the explosion of high-speed data services on the radio channel and resultant increase in average output power, the importance of the transmitter efficiency is emphasized even more. A variable PA power supply offers superior and unique performance benefits for improving talk time of mobile phones by maximizing utilization of battery power consumed.
This presentation reviews the technical advantages of implementing DCDC converters in mobile transmitters and discusses the relative efficiency and current consumption improvements. Recent advancements in power management design technology and system techniques to address the specific challenges in meeting multimode performance requirements will be discussed.
Senior member of Technical Staff at National Semiconductor, leads the system definition and architecture of RF power supplies for handset power amplifiers. Previously he has been in the forefront of innovation and development of Frequency Synthesizer, Femtocell, and RFIC wireless communications devices and architecture.
Yan-Fei Liu, John Shen, Shuming Xu
Anco Heringa
NXP
Netherlands
In many modern IC applications the supply voltage has to be converted to the lower voltage as needed by advanced CMOS technology. Preferably the power management enabled by HV-transistors, should be integrated with the advanced CMOS circuits in baseline CMOS technology offering a one-chip solution which guarantees cost competiveness and short time to market.
Both advanced CMOS at one hand and the high voltage transistors as needed in SoCs on the other hand have their own figures of merit with feature size and clock speed for CMOS and breakdown voltage, power handling, on-resistance and high frequency as key features for HV-transistors. We will show that the extreme feature size and process control from advanced CMOS can be exploited for the implementation of HV-transistors. By smart-layout of shallow trench, implants and poly/field plates HV-transistors can be realized in a base line state of the art sub-100 nm bulk foundry CMOS or PD-SOI CMOS process with figures of merit on par with transistors in special purpose HV-processes. Also the Hot-Carrier/reliability characteristics of these transistors, often being a major limiting factor, meet the requirements for a 10 year operational life time.
Anco Heringa
Anco Heringa graduated in technical physics at the University of Groningen in 1977.
From 1977-1987 he did research on medical physics and cardiophysics at the Catholic University Nijmegen. From 1987-2002 he was consultant in process, device and interconnect modelling in Philips Research and Philips Semiconductors. Since 2002 he is with Philips Research, now NXP Semiconductors, Leuven, Belgium, working on advanced CMOS and on integrated high voltage devices.
Jan Šonský
Jan Šonský has received MSc. in solid state physics at Czech Technical University in Prague, Czech Republic, in 1997 and his PhD degree at Delft University of Technology, The Netherlands, in 2002 on ultra-low noise silicon X-ray detectors. He joined Philips Research, now NXP Semiconductors, Leuven, Belgium, in 2002, where he has been working on integrated power management, RF power and SOI processes, and power conversion discrete technologies, including GaN. He serves on technical committees of ISPSD and IEDM, holds over 25 patents/patent applications in semiconductors and published on radiation detectors and high voltage and smart power technologies.
Shuming Xu
Texas Instruments
USA
In this presentation, a new device technology NexFET will be discussed. It improved the Figure of Merit (FOM) drastically, allowing high frequency operation, reducing the filter size. Scaling down to low voltage, NexFET shows great reduction of cost and better performance, promising two stage operation for MHz operation. The second generation NexFET is configured as source on the bottom of the substrate, allowing stacking the high side switch device on the low side synchronies device directly: this reduces the footprint by 50%, eliminates three parasitic inductors out of four. Furthermore, it removed the PCB parasitic resistance between the two devices in the traditional way. With the stack die power block, high frequency and small active block can be achieved simultaneously.
Shuming Xu, graduated from Jiaotong University, Xian China in 1982. Received his Master’s degree from Shaanixi Microelectronics Institute in 1987 and got the Ph. D from University of Bremen, Germany in 1997. Shuming worked in Daimler-Benz AG in Germany, IME in Singapore, Vishay Siliconix in CA, where he worked for power MOSFET development based on Trench technology. From 2001 to 2004, Shuming worked at Agere Systems and worked for RF LDMOS development. In the beginning of 2005, he co-founded a company called Ciclon Semiconductor and served as VP of technology. Where lead the development of NexFET. He is currently the Chief Technologist in Power Stage of Power Business Unit, Texas Instruments.
Paul Chow
Rensselaer Polytechnic Institute
USA
Switching regulators operating at 100s of Megahertz would enable high bandwidth power supplies capable of catering to the fast load transients especially in point of load converters in portable battery powered appliances. Such switching frequencies also allow for the use of air-core inductors, which can be integrated on chip or on package to minimize the form factor and achieve high power densities. However, the efficiency of hard-switched converters decreases drastically at these frequencies because of the gate driver and output switching loss in the power transistor, which are proportional to the gate charge of the FET used. Due to their improved material properties and device structure, GaAs pHEMTs, which are Schottky gate, field-effect transistors with a high mobility 2DEG channel, are shown to have a 2 to 4x advantage in figure of merit over silicon N-MOSFETs with the same voltage rating.
Enhancement mode low leakage pHEMTs are available through commercial foundries and are suitable for monolithic high frequency power supplies. We demonstrate a 4.5V input, 0.5-3.3V output, 1-2A multiphase buck converter in a 0.5um E/D pHEMT process with the power transistors, gate drivers and charge pumps integrated ON chip. A thick metal air-core coupled spiral inductor fabricated on a GaAs substrate is used in the output filter. The converter is capable of operating at a switching frequency of up to 200MHz and achieves a peak efficiency of 86%.
Professor, RPI
Dept. of Electrical, Computer and Systems Engineering
Education: B.A., Mathematics and Physics, Augustana College (S. Dak.); M.S., Materials Science, Columbia University; Ph.D., Electrical Engineering, Rensselaer Polytechnic Institute (RPI).
Experience: Dr. Chow was a member of the technical staff at GE-CRD from 1977 to 1989. Since 1989, he has been with RPI, where he is now professor of the Electrical, Computer and Systems Engineering Department. He has been working in the power semiconductor device area since 1982. His present research activities include novel device concepts, processing and circuit models for high-voltage silicon, GaAs and wide bandgap (particularly SiC and GaN) semiconductor power devices. He has published over 100 papers in scientific journals, has contributed seven chapters in technical textbooks, and has filed over fifteen patents. He is a fellow of the IEEE and a member of the Electrochemical Society.
Breakout Room
Sameer Pendharkar
Texas Instruments
USA
This presentation will focus on recent advances and innovations in mixed signal bicmos-dmos technologies that enable complex power SoCs as well as multi-chip power SiPs. Key performance metrics and robustness (short term and long term) criteria and characterization techniques will be presented. While the advances in lithography and processing help with SoC design, it also introduces challenges in monolithic integration of digital, analog, power and passives which drive new integration techniques and power device and esd design. The presentation will also touch on a few packaging techniques that enable SiP and help integrate disparate technologies to improve overall system performance.
Sameer Pendharkar graduated in Electrical Engineering at the University of Wisconsin-Madison in 1996 Since 1996, he has been at Texas Instruments Inc., Dallas, USA where he is presently a TI-Fellow and manager of high voltage and power component development team. His group’s main focus is defining integrated power roadmap and designing and developing high voltage and high power devices and ESD components for numerous BiCMOS and High Voltage CMOS technologies. He has published more than 50 papers and has more than 50 issued patents in the general area of semiconductor devices and processing.
Sami Ajram
SL3J Systems
France
The emergence low cost Chip Scale and Flip Chip packaging techniques for standard power ICs enabled a significant push of the switching frequency of DCDC converters and allowed several suppliers to introduce 4, 6, and 9MHz DCDCs that fit in a 6 mm2 PCB area. Designers start realizing that scaling the power switches becomes a complex equation that not only includes conduction and switching losses of the power switch but also wasted reactive power that stores in the extrinsic parasitics.
Complex PMICs based on 0.18um and 0.13um extended drain processes offer higher capabilities toward 50MHz to 200MHz switching frequency but the challenge is quite similar regarding the criteria for better scaling the power switches, reducing the die area, reducing the electrical overstress and managing the extrinsic power losses. The presentation provides simple rules and a simple theory that help the designer realize an optimum device scaling.
The most concerning challenge from design point of view comes from the controller that has to be radically changed because of the short on time duration and the difficulty on using blanking techniques due to the non-damped HF ringing after each power switching event. The presentation highlights the crosstalk mechanisms and suggests ideas and techniques for solving such issues.
Dr. Sami Ajram has 16 years experience in Electronics industry. He received his Ph.D. in 1998 from the University of Sciences and Technologies of Lille and pursued his research activities at the IEMN (http://www.iemn.univ-lille1.fr) pioneering 100MHz DCDC converter design based on IIIV power switches and PCB printed power inductors. He joined the ASIC department at ATMEL Rousset in 2000 where he led the design activity of HF clock synthesizers and low power front end sensors. In 2006, he joined Fairchild Semiconductor as Marketing Manager in charge of the development of High Frequency DCDC converters dedicated Dynamic Voltage Biasing of GSM / WCDMA RFPAs. He recently started SL3J SYSTEMS, a small design center focusing on Power Management and electronic solutions for handheld devices. He has 5 granted patents, published several papers and he received a Best Paper award from the IEEE PEL society in 2001.
Brice Jamieson, Ray Foley, Florian Herrault, Magali Brunet, Maeve Duffy, Yan-Fei Liu, José Cobos
Breakout Room
Charles R. Sullivan, Maeve Duffy, Matthew Wilkowski, Florian Herrault, Saibal Roy
Saibal Roy
Tyndall National Institute
Ireland
To enable the next-generation of highly-integratable, Power-RF magnetic components for on-chip converters, challenges must be
overcome in various facets, such as device design, modelling, next generation magnetic materials and integration. Accurate modelling
is the basis of any thorough understanding of the properties of a ferromagnetic thin-film, necessary to correctly predict the effects of
thin-film deposition in a miniaturized device. Starting from characterisations of as-deposited materials, analytic models are applied to
predict the effects of shape and thickness on the permeability of a structure. As well, the effects on inductance and loss at highfrequency
of a conductive seed layer have been analytically modelled, which is of particular necessity for electrodeposited conformal
thin-films.
To miniaturise the inductive components, magnetic materials are required which exhibit low loss at high frequencies. The features of
these materials must include a high anisotropy field, low hysteresis, high saturation flux densities and low eddy current losses. To meet
these requirements novel nanostructured magnetic materials are being synthesised. We have considered a number of different
electroplated, high-frequency nanostructured magnetic materials such as NiFe, CoNiFe, and CoP. Electroplating is compatible with the
deposition of conformal and relatively thick layers i.e. several µm to 10’s of µm to achieve required power density. However eddy
current losses due to the lower resistivity of the electroplated films mean that thick layers will have an inferior frequency response.
Typically, films are developed with pulse reverse plating to generate Co rich and Co deficient ‘multi-nano-layers’ having improved
saturation magnetisation and better frequency response. The plating parameters have been optimised in order to produce a material
with low loss and a high permeability of around 700 retained up to 103 MHz for a sample with a thickness of 1.7 µm, Bs of 1.2T and a
resistivity of 136µOhm cm. Some of the developed nano-materials have been integrated in the next generation of micro-inductors
fabricated at Tyndall.
1a) Schematic representation of a magnetic thin-film core illustrating components of anisotropy
1b) Measured and simulated anisotropy of a thin-film CoP layer as a function of sample rotation
2a) Wide-band complex permeability of a 1.7µm thick layer of Co91.5P8.5 Measured and simulated including Cu seed layer
2b) Image of fabricated micro-inductors at Tyndall National Institute
Dr. Saibal Roy is working as Senior Scientist in the Microsystems Centre of Tyndall National Institute, Cork, Ireland. He is Science Foundation Ireland Principal Investigator (SFI PI) and R&D leader in the Micropower – Nanomagnetics research area. He did his M.Sc. in Physics from the Indian Institute of Technology and received his Ph.D. working on advanced nanostructured materials from IACS in 1994. Since receiving his Ph.D, his professional experiences include 13 years academic and 3 years industrial research experiences; particularly he has served both in academia and industry as a senior scientist while leading research groups. Dr Roy’s present research interests at Tyndall include how engineered nanostructures could be employed for potential benefits for micron scale devices from beyond Moore (BM) to More than Moore (MtM) scenario. Since joining the Tyndall National Institute, Dr. Roy was able to bring substantial (€ 3.28 Million) government and corporate research funding. Recently Dr. Roy has been honoured by the president of University College Cork (UCC) for licensing the patented technology to INTEL. Some of his published work featured in BBC technology news; Daily Mail; Sunday Telegraph and in American radio. His recent microfabricated high frequency inductor work has been described as a global benchmark for integrated magnetics by NXP (PHILIPS). Dr. Roy has supervised several PhD and Post doctoral fellows at Microelectronics Dept., University College Cork, and at Tyndall National Institute. He has served as a member of several programme committees, chaired sessions and delivered invited talks in many International Conferences / Research Institutes. So far, he has filed 5 international patents, written 1 book chapter and published 94 papers with h index 14.
Donald .S. Gardner
Intel
USA
Rapidly increasing input current of microprocessors has resulted in rising costs and motherboard real estate occupied by the power delivery system. The current DC-DC converters on microprocessor motherboards are switching at or near KHz frequencies because of the strict efficiency requirements. Significantly higher frequency switching DC-DC converters in a CMOS process has been demonstrated for microprocessor power delivery [1-2]. The ultimate goal is to have a fully integrated converter with on-chip inductors to provide fine-grain power distribution and fast response time. On-chip inductors with magnetic material were integrated into both advanced 130 and 90 nm CMOS processes [3]. Increases in inductance of over 30 times corresponding to an inductance density of up to 1,700 nH/mm2 were demonstrated [4], significantly greater than air-core and other on-chip inductors with magnetic material. With such improvements, the effects of eddy currents, skin effect, and proximity effect become clearly visible at higher frequencies. The CoZrTa was chosen for its good combination of high permeability, good high-temperature stability (>250 °C), high saturation magnetization, low magnetostriction, high resistivity, minimal hysteretic loss, and compatibility with silicon technology. The CoZrTa alloy can operate at frequencies up to 9.8 GHz, but trade-offs exist between frequency, inductance, and quality factor. Techniques are presented to extract a sheet inductance and examine the effects of magnetic vias (vias that allow complete closure in the magnetic flux) on the inductors. The DC resistance is also important for converters and was 0.04 ohms with quality factors of 8 when using thick copper metallization and thick CoZrTa (see Fig. 1).
[1]G. Schrom, et al., “A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control,” in IEEE PESC, 2004, pp. 4702-4707 Vol.6.
[2]G. Schrom, et al., “A 100 MHz Eight-Phase Buck Converter Delivering 12A in 25mm2 Using Air-Core Inductors,” in Appl. Power Electronics Conf., 2007, pp. 727-730.
[3]D. S. Gardner, et al., “Integrated on-chip inductors using magnetic material (invited),” Journal of Applied Physics, vol. 103, p. 07E927, Apr 2008.
[4]D. S. Gardner, et al., “Review of On-Chip Inductor Structures With Magnetic Films,” IEEE Transactions on Magnetics, vol. 45, pp. 4760-4766, Oct 2009.
Donald Gardner has been with Intel Corporation since 1991 and is currently a Principal Engineer in Intel Research. He received his PhD in Electrical Engineering from Stanford University and is currently a visiting scholar at Stanford. Donald is the inventor or co-inventor of 64 issued patents including for inductors using magnetic materials, reflowed copper for interconnections, layered aluminum interconnections, and embedded decoupling capacitors. He has received Intel’s highest technical award “For Fundamentally Changing Platform Power Delivery with Integrated Voltage Regulators and Magnetic Inductors on CMOS”. Donald has published over 135 electrical engineering, materials science and computer science papers in journals and conferences. He has received three Best Paper and Poster awards at international conferences and over 1,700 authors have cited his publications. Donald invented a copper technology and used it to fabricate the first working chip with copper-based interconnections at Intel, then published on copper size effects that has been referred to as the first study that showed surface scattering and grain size to be a potential interconnect scaling issue. He pioneered techniques for the study of metallic films using in-situ mechanical stress measurements that are widely cited in the literature. He also invented an Al alloy/Ti metallization for interconnections as part of his PhD thesis studies that was later widely used by industry in microchips. Donald has had appointments as a visiting research scientist at Hitachi Research Labs in Japan and also at Stanford University. He enjoys bringing new life to old technologies by blending them with new scientific technologies or integrating them with new materials. His current interests include future microprocessor technology, magnetic materials for inductors, silicon-based optoelectronic devices, new materials integration and nanostructure design and devices.
Sarah Bedair
US Army Research Labs
USA
There is interest in power units with a single battery input and multiple output voltages for mobile micro-systems which are palm-sized and below [1]. Implementation of these units using larger COTS switched mode converters would cripple the entire system or limit functionality. Power converter size reduction motivates increasing the switching frequency (>20MHz), further reducing passive components’ size. An array of thin film, high frequency piezoelectric resonant transformers (PTs), each of which is impedance matched to various loads, is envisioned (Fig.1-top). The predicted performance (AC/AC, AC/DC) of PTs in a power converter is evaluated where electrodes may be lithographically defined for load impedance-matching. Although there are challenges with thin film PTs including depoling and power handling, they present a promising, alternate technology to thin film magnetic transformers where the magnetic material losses limit high frequency implementation.
A performance model of a 21.4MHz (190µm x 40µm x 11µm) length extensional thin film PT using lead-zirconium-titanate is presented [2]. The extracted series motional resistance, Rx, inductance, Lr, and capacitance, Cr, (Q=2023) are 50Ω, 0.75mH and 74fF, respectively [3]. The input/output electrode coverage is used to tailor to various loads and specifications including efficiency and voltage boosts. The performance may be tailored through decreasing the output electrode area which is traded for input electrode coverage (Fig-1). Although this comes at a cost of reduced electromechanical coupling, the tradeoffs in efficiency and boosts over higher Rx are superior under higher resistive load, lower power regimes where voltage boosts are desired. Expected performances are shown for various output electrode coverage, 100%*Lout/Lres. For example, if 50% efficiency can be tolerated, voltage boosts (normalized power delivered) of 3.53(156µW/V2), 3.47(750µW/V2) and 2.80(2.6mW/V2) may be achieved by designing the output electrode coverage at 100%*Lout/Lres=1%, 5% and 20% for loads of 80, 16 and 3kΩ, respectively. Simulations of the PT in an AC/DC configuration (Table-1) at the optimal frequency show that boosts up to 8.2 at 29% efficiency and 0.4% ripple may be achieved.
[1] B. Morgan, S. S. Bedair, W. Nothwang, D. Arnold, C. Meyer, B. Bowers, A. Sopeju, C. Dougherty, X. Lin, and R. Bashirulla, “Micro-power requirements & conversion for autonomous Microsystems” NATO Specialist Meeting on Energy Technologies and Energy Management for Portable Power Systems for Military Applications, Slovenia, May 2009.
[2] S. S. Bedair, J. S. Pulskamp, B. Morgan, and R. G. Polcawich, “Performance model of electrode tailored thin film piezoelectric transformers for high frequency switched mode power supplies”, PowerMEMS 2009, p. 435, Dec. 2009.
[3] H. Chandrahalim, S. A. Bhave, R. Polcawich, J. Pulskamp, D. Judy, R. Kaul, and M. Dubey, “Performance comparison of Pb(Zr0.52Ti0.48O3-only and Pb(Zr0.52Ti0.48O3-on-silicon resonators”, Applied Physics Letters, 93, p. 233504-1 (2008).
Sarah S. Bedair is an Electronics Engineer at the US Army Research Laboratory (ARL) in Adelphi, Maryland. Prior to joining ARL as an
employee, she was an Oak Ridge Associated Universities (ORAU) Postdoctoral Fellow. She received her B.S. (2002) degree in Applied
Sciences from the University of North Carolina at Chapel Hill. She also received her M.S. (2004) and Ph.D. (2008) degrees from Carnegie
Mellon University from the Electrical and Computer Engineering Department where she conducted research on CMOS-MEMS gas
chemical sensors and MEMS resonator / oscillators. During her studies she was awarded the UNC-Chapel Hill James D. Crawford Award
(2002) and the Phillip and Marsha Dowd-ICES Fellowship (2005) and was a member of the Phi Beta Kappa and Eta Kappa Nu honor
societies. She also received the 2010 Excellence in Federal Career – Rookie of the Year Award (Technical & Scientific) in addition to the
2009 Army Research Laboratory Research and Development Award. Her research interests include high frequency switched mode
power supplies, high frequency piezoelectric resonators / transformers and the fabrication of integrated MEMS passives.
Florian Herrault
Georgia Tech
USA
Traditional passive elements in power conversion technologies, inductors and capacitors, are comprised of combinations of electrical conductors and materials of high magnetic permeability or high electric permittivity. Microelectromechanical (MEMS) researchers have been working on integrating these structures with integrated circuitry for many years. More recently, MEMS technology is being utilized to improve the performance of the materials themselves. This presentation will give an example of the use of MEMS to improve the properties of passive elements. Specifically, we have developed highly-laminated metallic magnetic alloys with suppressed eddy current losses for high-frequency power converters.
Iron alloys are used as magnetic core materials for inductors at low frequency, due in part to their extremely high value of saturation flux density. However, at higher frequencies (such as the continually increasing frequencies of switching converters), induced eddy current losses make the use of iron alloys challenging. Ferrites are therefore used due to their high electrical resistivity, even though they have low saturation flux density, resulting in relatively bulky inductor cores. Although laminations can be used to suppress eddy currents in iron cores (and are, at power delivery frequencies such as 60 Hz), the thickness of laminations necessary to suppress these currents at switcher frequencies extends into the submicron range. Using MEMS technology, we have developed approaches to realize iron alloy cores with macroscopic total thickness built from many submicron laminations. These cores allow the use of high saturation flux density iron materials in switching converters, potentially greatly shrinking the size of converter modules.
and the Ph.D. degree in electrical and electronics engineering from the National Institute of Applied Sciences (INSA), Toulouse, France, in 2003, 2005, and 2009, respectively. However, his Ph.D. research was performed at Georgia Institute of Technology (Georgia Tech), Atlanta. He is currently a Research Engineer with the MicroSensors and MicroActuators Group, Georgia Tech. His current research interests include piezoelectric and electromagnetic actuators, small-scale power generation systems, high-performance magnetics for on-chip power converters, 3-D microelectromechanical systems (MEMS) fabrication, and MEMS-enabled thermal management devices.
Breakout Room
Nian Sun
Northeastern University
USA
Figure 1: Real and imaginary permeability spectrum of the CoZrTa/Al2O3 multilayers with a total thickness of 1.7 µm.
Figure 2: Permeability spectrum of Ni0.27ZnxFe2.73-xO4 thin film with x=0.03
Integrated magnetic inductors, magnetic transformers and RF magnetic filters, etc. require soft magnetic material that can be deposited at low temperatures and have a high permeability, large saturation magnetization, high resistivity, high ferromagnetic resonance frequency, low loss tangent, etc. In this presentation, we will cover our research on different metallic magnetic films and ferrite films deposited at near room temperature and their applications in integrated RF magnetic devices. These metallic magnetic films include FeCoN, FeCoHf, and CoZrTa/Al2O3 multilayers, etc. High saturation magnetization FeCoN films with a saturation magnetization of 2.4 T were developed with a high relative permeability of 1000, high ferromagnetic resonance frequency of ~2 GHz and a low coercivity of ~1 Oe. In addition, we investigated the composition gradient sputtering method for depositing a series of (FexCo1-x)1-yHfy alloy films with different Fe/Co atomic ratios and a small amount of Hf doping, which had a high saturation magnetization of 1.8 ~ 2.2 T. The compositional gradient of the Hf content in Fe-Co-Hf films led to a large in-plane anisotropy field of 200 ~ 500 Oe and a high ferromagnetic resonance frequency of > 7 GHz. We also investigated the magnetic properties of laminated CoZrTa/Al2O3 multilayer films with different periods and a total thickness of ~1.7µm, which show significantly enhanced performance at GHz frequency compared to single layer CoZrTa films with similar thickness. Besides metallic magnetic films, we also fabricated different NiZnCo-ferrite films with high µr in the GHz range through spin spray deposition at a low temperature of 90°C. The NiZn-ferrite films showed a low magnetic loss tangent tan∆m = µ”/µ’ of ~0.025 between 1~1.5GHz, and a high ferromagnetic resonance frequency of 2.7 GHz. At the same time we have designed, fabricated and tested different RF magnetic devices such as inductors, transformers and filters which showed excellent performance.
Nian Sun is an associate professor at the Electrical and Computer Engineering Department, Northeastern University. He received his
Ph.D. degree from Stanford University. Prior to joining Northeastern University, he was a research scientist at IBM and Hitachi Global
Storage Technologies between 2001~2004. Dr. Sun was the recipient of the NSF CAREER Award, ONR Young Investigator Award, USAF
Summer Faculty Fellowship, and the first prize IDEMA Fellowship. His research interests include novel magnetic, ferroelectric and
multiferroic microwave materials and devices such as antennas, filters, phase shifters, circulators, inductors, transformers, energy
harvesting technologies, magnetic sensors, solar cell materials and devices, etc. He has over 80 publications and has >20 patents and
patent disclosures.
Matthew Wilkowski
Enpirion
USA
Integration of the magnetic function with the power switches and control function for dc-dc converters has progressed significantly over the past twenty years. There have been numerous publications citing reduction of physical size with acceptable power efficiencies for dc-dc converters with the magnetic function implemented on silicon. With the existence proofs in place for the various fabrication and design methodologies, it is time to drive further improvements in cost, technology acceptance by proliferation of device designs into various applications and availability of certification and field reliability data etc., through commercialization of products.
The cost effective and successful commercialization of magnetics on silicon requires trade-offs between the obvious technical physical and electrical improvements and the constraints of the currently available manufacturing processes with an eye towards future process capabilities as market acceptance warrants the required investments.
Critical performance criteria such as small signal inductance, series resistance, saturation current and large signal ac power loss can be defined for inductor performance for specific levels of device performance as well as for specific combinations of materials, geometries and fabrication technologies. However these levels of performance must be sustainable through the temperature and physical stresses of wafer manufacturing process and the device packaging process. This requires verification of the critical inductor parameters through all stages of the manufacturing process as well as through industry recognized JEDEC device level reliability characterization programs in an effort to identify potential variations and shifts and their appropriate countermeasures.
The insights obtained from manufacturing and reliability characterization of the first generation of commercial devices can be applied to more complex second generation devices which involve greater levels of integration of materials and geometries.
Matt Wilkowski is Director of Magnetics and Components Engineering for Enpirion. In this role, Matt is responsible for the design and analysis, characterization and verification as well as reliability characterization of new and existing inductor designs and manufacturing technologies in PSIP and PwrSoC packages. Prior to Enpirion, Matt was Director of Component Engineering for Tyco Power Systems. During his tenure at Power Systems, Matt was responsible for the design and development of new magnetic structures for standardization throughout a broad product portfolio from first concepts based on electrical and physical requirements through manufacturing realization.
Matt has been involved with the design, characterization and qualification of discrete and integrated magnetic components for more than thirty (30) years. Throughout this involvement, Matt has been an active member of various professional organizations relative to magnetic and packaging. These include the Electronic Transformer Technical Thrust of the PELs Power Systems and Components Technical Committee, IEC TC 51 Magnetic Components and Ferrite Materials, PELs Standards Committee and PSMA’s Magnetics and Packaging committees.
Figure 1: Simulation Model
Figure 2: Local permeability extraction as a result of the proposed coupled analysis
It is important for a planar power inductor for one-chip DC-DC converter to keep required AC inductance under superimposed DC field defined by DC output current. This paper proposes a new design methodology to endure coupled analysis of magnetic hysteresis model and numerical electromagnetic (EM) field simulation to realize more smaller inductor [1]. The Jiles-Atherton static hysteresis model [2] is employed.
A 5.0 x 5.0 x 0.5 mm3 size planar rectangular spiral inductor is modeled in a commercial EM simulator (Maxwell 3D, Ansoft Co.), where 2-turn coil is sandwiched by 0.2mm thick MnZn ferrite layers, as shown in Fig. 1. The extracted J-A parameters are ; Ms=1.46×10-6, a=88, c=0.35, k=72 and alpha=0.00017. The conductor carries DC 1.1A and AC ripple 0.1Ap-p. Initially, permeability is assumed as non-linear and non-hysteretic with magnetic field intensity but uniform within the core space. After the first turn of the EM simulation, the permeability is replaced by position-dependent constants based on the J-A model depending on the simulated local flux density. This process was repeated for 9 times to be converged, as shown in Fig. 2. Flux density B on the coil (Cuboids 2 & 4) is B=0.43T and closely to saturation with relatively low permeability of µr=1600 whereas B=0.10T with µr=2300 at the edge of the inductor (Cuboids 1 & 5). Smaller inductor with improved DC-superimposed performance can be developed based on this method.
References:
[1] M. Yamaguchi, T. Inagaki, M. Furuta, Y. Lu and S. Muroga, Joint European Magnetic Symposia(JEMS) 2010, Soft-A-oral 370, August 2010, Krakow, Poland.
[2] D. C. Jiles, et al., J. Mag. Mater., 61 (1986) 48.
1984 Ph.D, Dept of Electrical Engineering, Tohoku University
1984 Assistant Professor, Dept of Electrical Engineering, Tohoku University
1991 Associate Professor, Research Institute of Electrical Communication, Tohoku University
2003 Professor, Dept of Electrical Engineering, Tohoku University
Academic Society Activities:
- 2010 Editor of the IEEE Transactions on Magnetics – Conference (Intermag 2010)
- 2003-2009 Program Committee member of the IEEE International Magnetics Conference (Intermag 2003 -2009)
- 2005-2009 Member of the Board of Directors, Co-Editor-in-Chief, the Magnetics Society of Japan.
- 2002 – 2008, General Chairman of the IEEE Magnetics Society 1st to 7th International Workshop on the high frequency micromagnetic devices and materials
- 2007 IEEE Magnetics Society Japan-Sendai Chapter Chair
Awards:
- 2010, 2004, 1986: Outstanding paper award, The Magnetics Society of Japan
- 2002 Award of the Society of promotion of Scientific measurements “High frequency magnetic field measurements using multilayer shielded-loop coil.”
Florian Herrault, Seth Sanders, Magali Brunet
Catherine Bunel
IPDiA
France
As the market for miniaturized devices continues to grow and expand , it has become evident that IPDIA has made the right choice to consider the 3D passive integration as a top priority. This IPD (Integrated Passive Device) provider is focusing its activities on 3D passive integration in Silicon with an advanced and unique technology called “PICS” (Passive Integrated Connective Substrate). High-density trench capacitors, MIM capacitors, resistors, high-Q inductors, Zener diodes are implemented in Silicon enabling their integration in various packaging technologies with active devices suitable for high power applications. In this paper, the PICS capacitors performance will be discussed and compared to the standard MLCC capacitors . The outstanding characteristics of IPDIA Silicon Capacitors , in terms of integration , electrical performance and reliability will be illustrated by several examples of applications. The technology roadmap towards higher densities will conclude the paper.
Catherine started her career in Philips in 1985. She worked in several departments in Process and Product Development and Manufacturing taking a new position every 4 years.
She was assigned as the Process Development Manager in Philips and then in NXP Semiconductors since 2004. . She drove innovation and developed the new technologies to create future “System-in-Package”, providing the support to the manufacturing and external manufacturing in Asia as soon as needed.
She is now the R&D director of IPDIA leading the innovation of Integrated Passive Devices for several market segments such as Medical, Industrial, Communications and Lighting . She manages a team of 20 Engineers and she drives the development of new technologies in partnership with European labs and Research institutes.
Catherine holds a degree from Ecole Supérieure d’Ingénieurs en Electronique et Electrotechnique (ESIEE) in Paris
Magali Brunet
LAAS CNRS, Toulouse
France
Supercapacitors also called Electrochemical Double Layer Capacitors (EDLCs), with a charge storage mechanism purely electrostatic are intermediate components between batteries and capacitors. In storage applications, despite lower energy density, they have the advantages over batteries of long life time (millions of cycles) and provide fast charge/discharge rates in a wide potential window and temperature range. In power applications, supercapacitors, despite their lower power than standard capacitors, have a high capacitance density that can make them interesting as energy reservoirs in various power integrated circuits.
We present here the integration of supercapacitors onto silicon substrate elaborated using electrophoretic deposition (EPD) of activated and onion-like carbon. We show that thanks to the design of the micro-electrodes, the carbon nanomaterial and the absence of organic binder and polymer separator in the process, the micro-devices can reach very high power densities (close to 1kW/cm3), of the same order of electrolytic capacitors while keeping a high enough energy density (10 mWh/cm3). These performance will be compared to actually available 3D integrated capacitors.
Magali Brunet obtained her PhD in Microelectronics Engineering in 2003, at the National Microelectronic Research Centre (NMRC, now Tyndall Institute), Cork, Ireland. After a post-doc in Leti-CEA in Grenoble in 2004, she joined the Laboratory of Analysis and Architecture of Systems (LAAS – CNRS), Toulouse, as a research scientist in the group Integration of Power Management Systems. Her research is focused on integrated passive components for power electronics (micro-inductors, micro-transformers, micro-capacitors) and for energy storage (micro-supercapacitors). She is looking in particular at the micro-fabrication technologies and the integration of new materials for these applications.
Mihaela Popovici
IMEC
Belgium
Strontium titanate (SrxTi1-xOy) perovskite films are highly attractive as high-k dielectric materials for dynamic random access memory (DRAM) applications in Metal-Insulator-Metal (MIM) capacitors due to their high dielectric constant allowing a high storage capacity. In view of 3-D structures envisaged for these applications to achieve ultra-high storage density, the most suitable technique is atomic layer deposition (ALD), which through its self-limiting growth mechanism ensures a conformal coverage. Strontium titanates (STO) can be obtained over a composition range between 45 and 67 % Sr using for example Sr(tBu3Cp)2 and Ti(OMe)4, as precursors. The cubic lattice cell can be modified by incorporation of an excess of Ti or Sr atoms varying Sr:Ti pulse ratio during film growth [1]. After crystallization anneals at temperatures above 550oC typically a perovskite structure is formed. Growth of the STO thin films was done on metals such as TiN, Ru or Pt that form the MIM bottom electrode. The films were investigated via X-ray diffraction (XRD), transmission electron microscopy (TEM), Rutherford backscattering spectrometry (RBS), X-ray photoelectron spectroscopy (XPS) and time-of-flight secondary ion-mass-spectrometry (TOFSIMS). The electrical performance of crystalline strontium titanates with different compositions was investigated via C-V and I-V measurements of MIM capacitor stacks using Pt or TiN as top electrodes. The dielectric constant (extracted from film thickness series) and leakage current strongly depend on the Sr/(Sr+Ti) content [2]. The leakage current density can be significantly lowered (without compromising the high capacitance densities) by stacking multiple dielectric layers, e.g. the use of a seed layer (thin STO layer crystallized before the ‘‘bulk’’ STO deposition) or a multilayer such as SrTiO3/GdAlO3/SrTiO3 [3].
1. M. Popovici, S. Van Elshocht, N. Menou, J. Swerts, D. Pierreux, A. Delabie, B. Brijs, T. Conard, K. Opsomer, J.W. Maes, D.J. Wouters, J.A. Kittl, Atomic Layer Deposition of Strontium Titanate Films Using Sr((Bu3Cp)-Bu-t)(2) and Ti(OMe)(4), Journal of the Electrochemical Society 157 (1) (2010) G1-G6
2. N. Menou, M. Popovici, S. Clima, K. Opsomer, W. Polspoel, B. Kaczer, G. Rampelberg, K. Tomida, M.A. Pawlak, C. Detavernier, D. Pierreux, J. Swerts, J. W. Maes, D. Manger, M. Badylevich, V.V. Afanas’ev, T. Conard, P. Favia, H. Bender, B. Brijs, S. Van Elshocht, G. Pourtois, D.J. Wouters, S. Biesemans, J.A. Kittl, Composition influence on the physical and electrical properties of SrxTi1-xOy-based metal-insulator-metal capacitors prepared by atomic layer deposition using TiN bottom electrodes, Journal of Applied Physics,106(9) (2009) 094101
3. N. Menou, M. Popovici, K. Opsomer, B. Kaczer, M.A. Pawlak, C. Adelmann, A. Franquet, P. Favia, H. Bender, C. Detavernier, S. Van Elshocht, D.J. Wouters, S. Biesemans, J.A. Kittl, Seed Layer and Multistack Approaches to Reduce Leakage in SrTiO3-Based Metal-Insulator-Metal Capacitors Using TiN Bottom Electrode, Japanese Journal of Applied Physics, 49 (4) (2010), 04DD01
Dr. Mihaela Popovici is currently researcher of the Thin Films Scientific Group at imec, Belgium. Her area of research includes atomic layer deposition of high-k oxides and metal gates. She is involved in designing metal-insulator-metal capacitors stacks, responsible for the dielectric materials development and physical characterization. She has a BS and MS in chemical engineering and received her PhD in Materials Science and Engineering in 2004, at the “Politehnica” University of Timisoara, Romania. After a two years post-doctoral stage in Philips Research Netherlands (Photonic Materials and Devices) she joined imec in 2007. Past research interests comprise magnetic nanocomposites and optical thin films development via sol-gel chemistry. She has authored or co-authored over 30 papers published in international journals and conference proceedings and holds 6 patents.
Stephen O’Brien
City College of New York
USA
Production of complex metal oxides for high k dielectric applications, either as gate dielectrics or in capacitor technology is commonplace. Requirements for integrated electronics are generally towards miniaturization, higher permittivity and dielectric strength, and lower loss/leakage. New sources of energy production (e.g. renewables, intermittant) will also require advances in energy storage and power conversion. Assembly of dielectric nanoparticles into thin films is a highly attractive means to produce composites with improved performance and tunability as a function of size, composition and structure. One of the major processing challenges is conversion of the nanoparticle building block into a reliable thin film device. Essential to this approach is an understanding of the chemical components and interface chemistry, combined with an ability to integrate them into thin films that have uniform and characteristic electrical properties. An attractive feature of this pursuit is the possibility to adapt large area deposition approaches, for example preparing printed capacitors. Our current process allows us to prepare capacitor thin films or gate dielectrics (particle/polymer composites) with dielectric constants k in the range of 10-60, over 100 kHz-1 MHz. Such methods aim to circumnavigate the need to develop complex fabrication tools normally associated with semiconductor manufacturing, and to make the process cheap and scalable.
Steve O’Brien is an established academic researcher in nanotechnology, with expertise in inorganic materials chemistry and materials science and engineering. He works on Nanoparticle synthesis and self-assembly. He is associate professor of chemistry at City University of New York, City College, and a faculty member of the CUNY Energy Institute. He is published in over 75 articles, and invented new methods for the preparation of electronic materials for the semiconductor industry and other areas of nanotechnology, with several pending patents. He was a Lindemann Post-Doctoral Fellow and an NSF CAREER recipient. Steve has a D.Phil from Oxford University.
Breakout Room
Ray Foley, Yan-Fei Liu, Eduard Alarcon
Rais Miftakhutdinov
Texas Instruments
USA
While the integration trend in low-power hand-held devices is very well pronounced and established, the benefits of PSiP and PwrSoC technologies are not so obvious for relatively high power non-isolated and isolated power systems. This topic considers PSiP and PwrSoC based functional blocks, optimal topologies and control strategies as part of power system with the output power up to few kW.
One example is high end micro-processors and DSPs where power supply integration into the package allows significant cost and number of decoupling capacitors saving by better handling extremely high di/dt transients of such digital processors. In case of isolated converters and inverters, the PSiP and PwrSoC technologies can find place as bias supplies for MOSFET/IGBT drivers and isolated active current and voltage sensors. Additionally, integrated magnetics can be part of conceptually loss-less resonant drivers for power switches.
Major challenges for PSiP and PwrSoC in the outlined applications are relatively high operating voltage up to 20V, currents up to tens amps in case of power supplies for microprocessors, and, in many cases, the need for the electrical isolation. The topic describes few possible solutions to address these challenges.
Dr. Rais Miftakhutdinov is a technologist and Senior Member of Technical Staff at Texas Instruments Inc., currently focusing into the area of power supply controller and driver ICs for high efficiency and power density power systems. He has graduated from Moscow State Aviation Institute, where in 1997 was awarded PhD Degree in Electrical Engineering without interrupting his work in the industry. Rais Miftakhutdinov shares with the audience his more than 30 years experience in Power Electronics field where he has been awarded 12 patents and published more than 40 papers, including presentations at Power Systems World, APEC, PESC and others.
Eby Friedman
University of Rochester
USA
The presentation is composed of three parts. First, a recently manufactured test circuit of a small on-chip point-of-load voltage converter will be described. This active filter-based circuit is a hybrid combination of a switching DC-DC voltage converter and a linear voltage regulator, exploiting active circuitry rather than the bulky passive devices typically used in a buck converter. The voltage regulator can supply over 140 mA current while exhibiting high current efficiency greater than 99% and achieves fast load regulation (72 ns) while requiring only 0.026 mm2 on-chip area. This circuit provides a means for distributing multiple local power supplies across an integrated circuit while providing high current efficiency. In the second part, simultaneous co-placement of these point-of-load power supplies with on-chip decoupling capacitors to improve overall signal integrity of the power grid will be discussed and the many highly complex interactions among the power supplies, decoupling capacitors, and load circuitry will be reviewed.
In the third part, a distributed voltage regulator designed and manufactured in a 3-D IC technology will be briefly reviewed.
Eby G. Friedman is a Distinguished Professor at the University of Rochester and a Visiting Professor at the Technion – Israel Institute of Technology. His research is in high performance synchronous digital and mixed-signal microelectronic circuit design. He is the author of almost 400 papers and book chapters and thirteen books in the fields of high speed and low power CMOS design techniques, high speed interconnect, and synchronous clock and power distribution networks. He previously was the Editor-in-Chief of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, a recipient of the University of Rochester Graduate Teaching Award, and a College of Engineering Teaching Excellence Award. Dr. Friedman is a Senior Fulbright Fellow and an IEEE Fellow.
Olivier Trescases
University of Toronto
Canada
Dynamic power consumption in the gate-drive circuitry limits the light-load efficiency of high-frequency, low-power integrated dc-dc converters. In this talk a power MOSFET gate-charge recycling technique is introduced, where the output capacitor is used to store a portion of the gate charge between switching events. The charge is transferred between the gate of power MOSFET and the output capacitor using transmission gates with precise closed-loop timing control. The timing of the charge transfer is regulated using a simple digital delay-locked loop in order to compensate for temperature and process variations. The converter is designed in 0.13 µm CMOS technology, and simulation results show a total saving of 25% in gate driver power and an overall efficiency improvement of 5%. The converter operates at 20 MHz and converts 2.5 V to 0.8 – 1.6 V at up to 300 mA.
Olivier Trescases is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Toronto, where he received his Ph.D. degree in 2007. Dr. Trescases’ past research topics include high-efficiency switch-mode power supplies, quasi-resonant dc-dc converters, dynamic voltage/frequency scaling in VLSI circuits, all-digital class-D audio amplifiers and motor drives for hybrid electric vehicles. From 2007 to 2008, Dr. Trescases worked as a concept engineer at the high-integration group at Infineon Technologies AG. He has received two IEEE best-paper awards in 2003 and 2006. Dr. Trescases’ current research group focuses on high-efficiency power converters for industrial, automotive, aerospace and renewable energy applications.
Workshop BanquetSponsored by:
United Technologies Research Center
Ray Foley, Yan-Fei Liu, Eduard Alarcon
David Anderson
National Semiconductor
USA
The move to higher switching frequencies facilitates the use of physically smaller filter components that are a requirement for full integration of switching converters, but introduces numerous challenges for controlling frequency-dependent loss mechanisms. This paper will review the capabilities and limitations of integrated power inductors and will examine the application of various circuit control topologies to explore the possibility of a sweet-spot for a cost-effective yet efficient PSOC.
David Anderson is a senior technologist, working in National’s research laboratory on advanced power management development. He received his BSc (Hons) degree from Edinburgh University in 1968. He has spent a long and distinguished career in the electronics business and often provides unique insights on the various panels and forums he participates in as technology guru.
David’s first role was Design Engineer at Nuclear Enterprises in Edinburgh, working with a team developing a portable X-ray spectrometer for mineralogy application. After Nuclear, he joined Ferranti Electronics to work on telemetry systems and later joined Siemens in Munich, Germany where he developed analog integrated circuits for audio, video and camera applications.
Returning to Scotland in 1978, David joined National Semiconductor in Greenock, where he developed audio ICs, including analog Telecom and Dolby Noise Reduction ICs. In 1991 he moved to National’s headquarters in Silicon Valley as Design Manager for Automotive IC Development and was responsible for the development of over 40 automotive IC’s.
In 1996, he joined Semtech Corporation as Vice President of Engineering where he established and grew Semtech’s Power Management Development Group before moving to a start-up company, Volterra, in 2001 as Vice President of Engineering. Volterra has pioneered integrated switchers utilizing mixed-signal control topologies and achieved industry-leading power density for fully integrated power switchers utilized in computers and POL [point-of-load] regulators.
In 2004, David returned to his roots at National Semiconductor in Santa Clara, California as Chief Technologist for Power Management. Working in NS Labs , National’s research and design laboratory, David’s current focus is on advanced semiconductor and power control topologies that show potential to transform existing IC systems. In this role he is involved in a wide gamut of power circuits that range from milliwatts to kilowatts, with a strong emphasis on alternative energy systems.
Seth Sanders
UC Berkeley
USA
Technical merits and challenges of the switched capacitor approach to dc-dc power conversion are discussed. A detailed analysis enabling a strategic comparison among switched-capacitor converter topologies and also enabling comparison of switched-capacitor topologies with conventional magnetic topologies is outlined. The analysis framework allows a quantitative comparison of the various popular power conversion circuits in terms of their utilization of switch technology and also their utilization of energy storage devices (eg. capacitors, inductors). Significantly, the analysis shows that for a wide range of conversion applications, switched capacitor converters should be expected to outperform the conventional buck, boost, and transformer-based converters with respect to component utilization. Since switched capacitor converters contain no magnetic devices, they are well suited to integration in a range of CMOS processes. Further, since devices can be effectively stacked, extended voltage operation can be realized with low voltage processes.
However, switched capacitor converters also present a number of challenges in voltage regulation and in ripple performance. Design strategies to meet these challenges, and to exploit the excellent potential of switched capacitor dc-dc converters are outlined. Examples of on-die multi-core VR conversion, board-level point-of-load conversion, and ultra-low-power on-die conversion for wireless sensor applications will be discussed.
Seth R. Sanders is a Professor of Electrical Engineering in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. He received S.B. degrees (1981) in Electrical Engineering and Physics, and the S.M. (1985) and Ph.D. (1989) degrees in Electrical Engineering from the Massachusetts Institute of Technology, Cambridge. Following an early experience as a Design Engineer at the Honeywell Test Instruments Division in 1981-83, he joined the UC Berkeley faculty in 1989. His research interests are in high-frequency power conversion circuits and components, in design and control of electric machine systems, and in nonlinear circuit and system theory as related to the power electronics field. Dr. Sanders is presently or has recently been active in supervising research projects in the areas of flywheel energy storage, novel electric machine design, renewable energy, and digital pulse-width modulation strategies and associated IC designs for power conversion applications. During the 1992-1993 academic year, he was on industrial leave with National Semiconductor, Santa Clara, CA. Dr. Sanders received the NSF Young Investigator Award in 1993 and multiple Best Paper Awards from the IEEE Power Electronics and the IEEE Industry Applications Societies. He has served as Chair of the IEEE Technical Committee on Computers in Power Electronics, and as a Member-At-Large of the IEEE PELS Adcom. He is an IEEE Fellow. More information available at www.power.eecs.berkeley.edu
Gabriel A. Rincón-Mora
Georgia Tech
USA
Wireless microsensors and other miniaturized electronics cannot only monitor and better manage power consumption in emerging large-scale applications for space, military, medical, agricultural, and consumer markets but also add energy-saving and performance-enhancing intelligence to old, expensive, and difficult-to-replace infrastructures. The energy these small smart devices store, however, is often insufficient to power the functions they incorporate (such as telemetry, interface, processing, and others) for extended periods, and replacing or recharging the batteries of hundreds of networked nodes is prohibitively expensive. Harvesting energy from the surrounding environment to continually replenish a battery is therefore an appealing alternative, even if the development of relevant technologies today is at its infancy. This seminar illustrates the means by which microelectronic semiconductor switching converters can harness energy and condition power from miniaturized piezoelectric and electrostatic transducers that transform kinetic energy in vibrations into the electrical domain. The presentation introduces and describes how power-conditioning stages and control circuits draw and direct derived energy into a battery and shows the experimental results obtained from integrated-circuit (IC) prototypes.
Prof. Rincón-Mora worked for TI in ’94-’03, was Adjunct Professor for Georgia Tech (GT) in ’99-’01, and is a tenured professor at GT since ’01. His scholarly products include 8 books, 1 book chapter, over 125 scientific publications, 27 patents, over 26 commercial chips, and over 55 speaking engagements. He received the “National Hispanic in Technology Award,” “Charles E. Perry Visionary Award,” a “Commendation Certificate” from the Lieutenant Governor of California, IEEE Service Award, and Robins Air Force Base’s “Orgullo Hispano” and “Hispanic Heritage” awards and was inducted into GT’s “Council of Outstanding Young Engineering Alumni.” He is an IET Fellow, IEEE Distinguished Lecturer; TCAS II Associate Editor; JOLPE Editorial Board Member, and SSCS-CASS Chapter Chair.
Arnold Alderman, Baoxing Chen, Cian Ó Mathúna
This presentation provides a summarized overview of the product development the market drivers enabling these devices to become mainstream integrated power converter products. PSiP device performance trends and events will be discussed covering the past 2 years since the PowerSoC 2008 Workshop. These trends include improvements in current density, efficiency, switching frequency, cost reduction, higher functionality multiple conversion, and other key parameters. This presentation provides a wide perspective of the spectrum of variously integrated power management devices. The complementary role of devices such as power ICs, power management units (PMUs) and power PMUs (PMUs with power transistors) and system on chip (SoC) are put in perspective. This dissertation gives the attendee insight regarding future product trends including the expected advent of high voltage (off-line) ac-dc conversion integrated devices and introduction of fully integrated PwrSoC devices. Present PSiP and PwrSoC market size and expected market growth will be discussed highlighting possible key market enhancement and barriers. Material for this presentation is based on extensive market research conducted over the past 5 years. Former work in this area of study was published by PSMA in 2007 and 2009 with highlights and updates presented at PowerSoC 2008 and APEC 2009 and APEC 2010. The author is presently conducting research to update previous work. This most recent information will be included in the presentation.
The bio for this speaker will be available in the near future
Bill Liu
Analog Devices
USA
Power management has been the largest market of analog integrated circuits. With the conflict of the exponentially increased data processing and limited improved battery capacity, efficient energy management and further power reduction is rising to be the most important consideration for portable applications. The mass, public portable devices lead to the requirement of light weight, small volume, low cost as well as long battery lifetime, which challenges the system power management. This paper will try to cover several advanced power management IC techniques for portable applications. (a) The single-inductor multiple-output (SIMO) solution provides multiple regulated outputs by a single inductor. It has the merit of reducing external inductors. (b) Higher switching frequency results in smaller filter inductor and capacitor, furthermore the bulky passive components can shrink to be integrated on chip. (c) Nowadays electronic systems are so complex that a smart partitioning of battery energy management and power conversion is required. This drives the development of power management units (PMU), which are well defined integrated mixed signal circuits for specific customers. (d) The pursuit of high efficient power usage in each block level circuitry leads to more power management functions being embedded inside chip, e.g. audio amplifiers. (e) The solution of system in package (SiP) could optimize the trade-off among process, performance, board space and cost for many power management systems. This talk will also address and explore its future development and opportunities.
Bill Liu works in Analog Devices as director of Shanghai Design Center and Communication Infrastructure Asia Technical Groups with over 15 years experience in Semiconductor industry, mainly focus on analog and mixed signal product developments including linear amplifier, data converter, power management and high efficient switching amplifier and MEMS ASIC… published several patents, international conference papers and served as sub chairman, panelist and technical committee member in international conferences like A-SSCC, ISSCC and APCCAS…Profound international working experience in Japan, US and China, worked in TI, Burr-Brown and Fujitsu before.
Breakout Room
Dion Manessis
Fraunhofer Institute
Germany
Embedding of semiconductor chips into organic substrates allows a very high degree of miniaturisation by stacking multiple layers of embedded components. Among its merits, it provides superior electrical performance by short and geometrically well controlled interconnects as well as a homogeneous mechanical environment for the chips and thus resulting in superior reliability. By exploiting conventional PCB manufacturing practises, this paper will show how component embedding can be implemented in industrial 18”x24” organic substrate formats for large scale system-in-package manufacturing. Embedding allows to have conductors not only under but also over a component leading to a 3-dimensional packaging also on top of the embedded components. The component can be electrically connected to the top or to the bottom conductive layer or to both of them, e.g. in case of power ICs with contacts on both sides. Such embedding approach is very beneficial in the case of power Dies for enhanced heat dissipation from the backside of the power die. The Embedding process flow will be thoroughly discussed and results on embedded power MOS dies having a thickness in the range of 150-300µm will be shown. The resultant system-in-packages with embedded power die can be ultimately assembled as conventional SMD packages.
Dion Manessis possesses M.Sc and Ph.D degrees in Materials Science from Stevens Institute of Technology, USA and has also acquired technology and project management certificate degrees from Cornell University. Since 2001, he is working as Principal Technology Scientist in Fraunhofer IZM Berlin in close collaboration with the Microperipheric Research Center of Technical University Berlin. He is project manager for EU and industrial projects. His main R&D interests lie on Flip chip and Wafer Level CSP bumping, solder balling, printing of polymeric materials for wafer level packaging. The last 4 years, he has focused on component embedding technology implementation for manufacturing of miniature system-in-packages for advanced technological applications.
Brian Molloy
Infineon Technologies
USA
Infineon is a market leader in Power Semiconductors. The focus at Infineon is energy efficiency, system miniaturization in high volume applications such as computing. Ongoing research into PowerSiP and PowerSoC is focused on a right-fit approach. Further miniaturization is compelling in certain applications but may be overkill for others. High volume manufacturability with acceptable yield must be a consideration from the concept stage to satisfy any high-volume market. Many key markets have multi source requirements where unique single source solutions will find resistance. This presentation will discuss how these factors are taken into consideration at Infineon.
Brian Molloy is Director of Business Development for Infineon’s low-voltage DCDC controller and integrated power stage business. He received his BE (Hons) degree from the National University of Ireland (Galway) in 1987. Brian’s background is in mixed-signal power ASIC and ASSP development covering over 20 years in Design, Applications and now Business Development roles with Digital Equipment Corporation, Quantum, Seagate, MicroLinear, ST and now Infineon. Brian’s current focus is on DCDC for the PC and Server market.
Ashraf Lofti
Enpirion
USA
Enpirion continues to be a pioneer in commercializing PowerSoC technology, for this presentation,
Enpirion will highlight corporate advancements towards a full power system on a chip (PwrSoC) from
Enpirion’s historical and future perspectives. With a strong focus on market applications driving its
adoption as well as manufacturing enablement, the design, development and production of a PwrSoC is a continuously evolving effort towards the ultimate fully-monolithic single chip power system. Enpirion will present significant milestones in this development path and how it intends to implement commercialization efforts for many years to come.
Ashraf is the President, Chief Technology Officer and Founder of Enpirion. Ashraf has been continuously involved in research, design and commercial development in the power field for over 20 years
Prior to founding Enpirion, he led the power management R&D effort at Bell Laboratories as Director of Power Management Research (Lucent/Agere). During this period he laid the vision for a research effort with the ambitious goal of creating the technology pieces needed to create, for the first time, true power management on a single chip.
These efforts combined multiple disciplines from power semiconductors, RF circuits, high-speed power topologies, magnetic design to package technology in a highly coordinated development to achieve a commercially viable yet breakthrough technology enabling high performance in a single chip in an economical manner. Prior to that as Department Head, Power Systems Research, his development efforts in power systems applications ranged from high-density dc/dc power modules to planar high density magnetics to custom dc/dc converters to high power rectifiers and battery plants for telecommunications energy supplies. These technologies and others formed the cornerstone for many product lines delivered by Lucent’s (previously AT&T’s) Power Systems Division driving highly differentiated products in the market place commanding leadership market share and revenues. He also held various engineering and instructor positions at Virginia Tech and Cairo University.
Satoshi Matsumoto
Kyushu Institute of Technology
Japan
The climate changes bring the human race a lot of disadvantages. Japan is positively grappling with this problem. For example, in 2006, the Japanese Ministry of Economy, Trade, and Industrial issued its “Ultra-long-term Energy Vision in Japan” which stresses the importance from fossil fuel based energy sources to electrical energy. The effective use of electric energy is one of the most promising candidates to confront climate change. In such situation, the power electronics becomes a key technique. In future power electronics, we will utilize a lot of numbers of miniaturized DC-DC converters to use the electrical energy effectively. In this paper, I describe the example of the effective use of a electrical energy using a lot of number of the DC-DC converters. In addition, I also talk about how we can implement the semiconductor devices with passive devices on the same chip based on my past researches.
Satoshi Matsumoto received the B.S., M.S., and Ph.D. degrees in applied chemistry from Waseda University, Tokyo, Japan, in 1982, 1984, and 1996, respectively.
In 1984, he joined Nippon Telegraph and Telephone Corporation (NTT) LSI Laboratories. In 1993, he transferred to NTT Energy and Environments Systems Laboratories, where he has been engaged in research and development of analog high frequency devices and circuits, and environment friendly power electronics. In 2010, he moved to Kyushu Institute of Technology, Fukuoka, Japan. His current interests are power devices and IC’s and environment friendly power electronics.
